Freescale Semiconductor /SKEAZN84 /FTMRE /FCLKDIV

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Interpret as FCLKDIV

7 43 0 0 00 0 0 0 0 0 0 0 0FDIV0 (0)FDIVLCK 0 (0)FDIVLD

FDIVLD=0, FDIVLCK=0

Description

Flash Clock Divider Register

Fields

FDIV

Clock Divider Bits

FDIVLCK

Clock Divider Locked

0 (0): FDIV field is open for writing.

1 (1): FDIV value is locked and cannot be changed. After the lock bit is set high, only reset can clear this bit and restore writability to the FDIV field in user mode.

FDIVLD

Clock Divider Loaded

0 (0): FCLKDIV register has not been written since the last reset.

1 (1): FCLKDIV register has been written since the last reset.

Links

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